As demand for ever-shrinking semiconductor devices continues to increase, it has become particularly difficult to continue shrinking semiconductor devices, such as memory, due to rapidly increasing costs associated with lithography and multiple process steps associated with pitch splitting techniques.
Vertical memory, such as 3D or vertical NAND (VNAND) memory, appears to be a promising direction for increasing memory density. Implementation of 3D or VNAND includes building transistors (bits) vertically, rather than orienting memory structures in a planar manner. Early VNAND devices have 16 to 24 vertical bits with future plans to vertically extend to 48 and 64 bits. These changes are achieved with fewer process steps, relaxed lithography sizes, and lower manufacturing costs, as compared with the planar approach.
Various inspection systems are used within the semiconductor industry to detect defects on a semiconductor reticle or wafer. However, there is a demand for improved semiconductor wafer inspection systems for implementation with vertical semiconductor devices, such as 3D or VNAND memory.